资源列表
sram读模块基于FPGA的实现
- sram读模块基于FPGA的实现 verilog源代码,sram
sync(shipintongbuxinhao).rar
- 基于QuartusII环境下以模块化的形式做成的视频复合同步信号。,QuartusII-based environment to create the form of modular composite video sync signal.
decode.rar
- 基于VHDL语言的循环码编码器的程序，以一个（15，6）循环码为例,VHDL language based on the cycle of the program code encoder to a (15,6) cyclic code as an example
hssdrc_latest.tar.gz
- HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is li
squareroot.rar
- vhdl源代码,可以开16比特的平方根，算法简单，速度快,this is a vhdl code for square root
verilog.rar
- 《数字信号处理的FPGA实现》（第二版）光盘verilog代码," The FPGA digital signal processing to achieve" (second edition) CD-ROM code verilog
FPGA.rar
- 24秒倒计时设计用于专业篮球比赛有说明和一系列程序代码,24 seconds countdown designed for professional basketball game and a series of procedures has made it clear that the code
interleaver-vhdl.rar
- VHDL编写的基于FPGA的4-8交织器代码，有需要的下来看看,4-8 prepared VHDL code interleaver
zhuanpan.rar
- 增量式光电编码器输出四分频脉冲计数，分别为A，B两路信号,Incremental optical encoder pulse count output frequency of a quarter, namely A, B two-way signal
TFT-TGB-CONTROL.rar
- TFT-LCD-RGB的控制驱动显示程序,LCD_RGB CONTROL
1553_enc_dec.rar
- 1553B编解码程序 verilog 描述,1553B codec procedures described in verilog
vhdlCompetition.rar
- 用VHDL设计四人抢答器,vhdl学习的基础，很好用,vhdl competition