资源列表
uart_niosII.rar
- 基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！,Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!
trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
Manchester.rar
- 曼彻斯特编解码源代码,还包含曼彻斯特码的说明文档,Manchester Encoder-Decoder
fir.rar
- fir滤波器，Verilog语言写的，容易看懂,fir filter, Verilog language written in easy to understand
hw8.rar
- Verilog中经典的自动售货机的源代码，包含测试程序,Vending machine in the classic Verilog source code, including test procedures
frame_synchronization.rar
- 检测巴克码实现帧同步传输，vhdl语言，帧头,Detection of Barker code transmission to achieve frame synchronization
cos.rar
- 原创：cos函数和sin函数的VHDL实现，很实用,cos of the VHDL implementation
AHBtoAPB.rar
- amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc,amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc
vhdl
- 本设计中应用硬件描述语言Verilog HDL描述相位累加器，相位调制器，正弦波、方波、三角波、心电波形四个独立的波形存储器，并描述频率控制、相位控字、幅度控制单元及波形切换等相关的功能单元。-Application of the design described in Verilog HDL hardware descr iption language phase accumulator, phase modulator, sine, square, triangle wave, the fo
DDS
- 用Verilog编写的DDS逻辑,很好地实现了DDS功能，可以产生各种频率的正弦波。-DDS which was write by Verilog。
2point_data
- 基于Quatusii的两点非均匀性校正的VHDL程序，用于红外图像的预处理-Quatusii based on two non-uniformity correction in the VHDL program for infrared image preprocessing
config_ad9957
- 用Verilog正确配置ad9957，，在ISE环境中正确编译与实现-Properly configured with the Verilog ad9957,, compiled in the ISE environment and realization of the right