- EcosystemSim 生态系统模拟
- interlaced HMD 3D 头盔可以显示的程序
- chuansheng 一个仿照网络蚂蚁的一个网络下载程序
- VCDIP_P563 在visual c++中
- projectfiles its pure sine wava inverter source file in hez
- objectmarker ObjectMarker is a tool which lets you easily create an info file from your collection of images that contains your object you want to train.
资源列表
VHDL_digital
- 《数字系统设计与VerilogHDL》 阐述数字系统设计方法，重点对用vhdl设计开发常用的数字电路和数字系统进行具体阐述，配合大量设计实例。-err
ARM7_verilog
- arm 7 verilog code used setup soc
fifo
- 先入先出缓冲存储器，采用verilog hdl-FIFO buffer memory, using verilog hdl
UART
- 基于FPGA的UART实现 用VHDL编程-The UART-based FPGA using VHDL Programming
1553_enc_dec
- 1553b的编解码源程序 和仿真程序，fpga来实现的 vhdl语言 -1553B codec source code and simulation procedures, fpga to achieve the VHDL language
fanzhen
- vhdl代码： 出租车计价器VHDL程序与仿真！初学fpga者可以参考参考！！比较简单-VHDL code: Taximeter VHDL procedures and simulation! FPGA beginner can reference a reference! ! Relatively simple
fpgaPCI
- fpga开发pci的verilog，不可多得的源代码。-FPGA development pci of verilog, rare source code.
pre_norm_addsub
- 一种用VHDL语言描述的浮点前规格化的源代码编程-VHDL language used to describe a floating-point before the standardized programming source code
ssz
- 数字钟，用VHDL写的各个模块，顶层用图形编辑，在实验箱上完全通过-Digital clock, using VHDL written by various modules, top-level graphics editing, in the experimental box completely through
project_UHF_ddc
- vhdl语言写的数字下变频的实现，整个工程文件，xlinx ise用的-VHDL language written in the realization of digital down conversion, the whole project file, xlinx ise used
add
- Verilog hdl语言 常用加法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used adder design, can use the ModelSim simulation
divide
- Verilog hdl语言的常用除法器设计，可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation