资源列表
FPGA_UART
- FPGA实现UART串口通信协议 采用VHDL语言，顶层文件采用原理图的方式，简洁直观-FPGA Implementation of UART serial communication protocol
SRAM
- 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
static-timing-analyze
- 特权同学主讲的FPGA设计的时序约束专题（STA部分）-Speaker privileged classmates timing constraints for FPGA design topics (STA section)
itc99-poli2-vhd.tar
- VHDL source code of the ITC -VHDL source code of the ITC 99
斐波那契数列Verilog实现
- 斐波那契数列Verilog实现
myproj
- 使用vhdl语言设计波形发生器，产生正弦波，方波，三角波，锯齿波，实现频率，幅度可调。项目包附有设计说明和资料。-Waveform generator using vhdl language design, produce sine, square, triangle, ramp, realize the frequency, amplitude adjustable. Project package with design specifications and data.
sram_test
- is61lv25616简单的verilog程序，完成sram读写-is61lv25616 simple verilog program, complete sram read and write
BASYS2_CLOCK
- 基于xilinx basys2开发板 实现数字钟功能-Development board based on xilinx basys2 digital clock function
DDS_dac9764
- verilog语言编写的DDS信号源，采用DAC9764-verilog DDS signal source language, using DAC9764
select1
- 用VHDL语言实现多路数据选择器，测试仿真通过-VHDL language with multi-channel data selector, test through simulation
dds_double_new
- FPGA用verilog语言编写的 dds程序，两路输出，频率可调，相位可调，输出波形可调-FPGA using verilog language dds program, two outputs, adjustable frequency, phase adjustable, adjustable output waveform
zs
- 基于fpga的数字频率计，verilog编写，可修改闸门宽度0.1s/1s/10s，可测频率1hz~1mhz，包含整个工程，内部分频模块为了仿真方便改小了，后面注释为50mhz晶振下的分频值，可根据需要自行修改-Fpga-based digital frequency meter, verilog prepared to modify the gate width 0.1s/1s/10s, measurable frequency 1hz ~ 1mhz, contains the entire