资源列表
PPC_VME-2.0
- 基于PowerPC和FPGA开发的VME控制器的VME接口，采用SOPC建立环境，利用Verilog开发了接口时序。-PowerPC-based and FPGA development VME VME controller interface, using SOPC build environment, the use of Verilog developed interface timing.
my_bayer2rgb
- 摄像头Bayer 转rgb信号 用verilog 编写 在xilinx fpga 软件下 ise 综合 编译-Bayer turn the camera rgb signal in xilinx fpga verilog prepared under ise integrated compiler software
std_ovl_v2p7_Feb2013
- 目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下-The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.
NCO
- 查表法实现NCO数控振荡器，16位频率控制字深度1024，包含ROM表-nco rom
UART
- FPGA实现串口的收发，可以改波特率。Verilog HDL语言-FPGA Verilog HDL
i2c_reg
- 用verilog实现的一个从机的I2C通信模块，测试通过可用，已经在项目用的了！-Using verilog achieve a slave I2C communication module, the test is available, has been used in the project!
usrp-fpga-mirror
- usrp1的FPGA源代码，需要的可以研究研究-usrp1 of the FPGA source code, need to be studies
fpga_counter
- 光栅尺的计数，串口发送与继电器控制程序，无线通信-Grating count, serial transmission
dac
- 运用ISE13.2完成的DAC工程。完成一个数模转换的作用。-Use ISE13.2 completed DAC works. To complete a digital-analog conversion effect.
16bits_multiplier
- 这是一个有符号的16位乘法器的设计，包含详细的设计报告和全部的verilog代码。乘法器采用booth编码，4-2压缩，超前进位结构-This is a signed 16-bit multiplier design, detailed design reports and contains all of the verilog code. Multiplier using booth encoding ,4-2 compression, lookahead structure
state_machine-for-charging
- 利用有限状态机实现的投币式充电仪的模拟电路-Finite state machine coin-charging instrument analog circuits
data_recovery
- 通过数据恢复时钟的例子教程，对研究这类原理很有帮助哦-data clock decover xilinx example