资源列表
mult-64bit-booth.txt
- 64位booth乘法器，verilog HDL， zip文件，modelsim测试通过-64 booth multiplier, verilog HDL, zip files, modelsim test
huxideng
- 基于VHDL的呼吸灯设计， 可设置4个频率分别为0.1 ，0.2，0.4 0.5MHZ，quartus软件亲测可用-VHDL-based design breathing light can be set to four frequencies were 0.1, 0.2,0.4 0.5MHZ, quartus software pro-test available
ADS1271
- VHDL的接口程序 24-bit 105ksps ADC 型号是：ADS1271 绝对稳定-VHDL interface program 24-bit 105ksps ADC models are: ADS1271 absolutely stable
Design
- 基于FPGA的64QAM调制解调进行了研究和验证-64 qam modulation demodulation based on FPGA is studied and validated
SPI-Master-Core-DAC-ADC-spartan
- SPI Master Core for spartan (ADC, DAC) vhdl code
SineWAve
- xilinx system generator DAC simulink system code for black box
mux16
- 基于FPGA的verilog编写的乘法器-FPGA-based multiplier verilog prepared
FPGA_DDS
- FPGA控制AD9854产生FSK信号，硬件为ALTERA FPGA，单频点，亲测，Ok-fpga control the AD9854,generate FSK signal,ok
inv_matrix
- 矩阵求逆模块硬件实现,用verilog语言，基于ISE开发环境-implement of inverse matrix
24
- 基于6M晶振FPGA的篮球24秒计时器verilog HDL代码，附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
ins_Decoder
- 采用VHDL语言编写的矩阵变换器四步换流程序-matrix converter
can_latest.tar
- 基于Verilog的CAN控制器的IP核，可以参考-The CAN controller IP core based on Verilog