资源列表
pingpang
- FIFO读写，用使用状态机完成两片FIFO读写，乒乓操作。-FIFO read and write, using the state machine complete with two FIFO read and write, ping-pong operation.
calculator
- 用VHDL在quartus2下实现的计算器。输入为4*4矩阵键盘，输出为共用数据线的数码管。可以实现简单数学运算、逻辑运算、进制转换、连续运算等功能。-Using VHDL in quartus2 achieve calculator. Input 4* 4 matrix keyboard, the output data lines for sharing of digital control. Can achieve a simple mathematical operations, log
DDC_DUC
- 数字上下变频FPGA设计的详细介绍资料，还是中文的。很舍不得上传的哦。-FPGA digital down conversion design detailed information, or Chinese. Oh, very reluctant to upload.
Walsh
- 利用ISE编写的产生WALSH码的verilog程序，简单易懂，稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码-Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16，32，64-bit code WALSH. .
VHDL语言写的简易计算器
- 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
iscas89_verilog
- Verilog HDL 时序基准电路 ISCAS89-ISCAS89 sequential benchmark circuits Verilog HDL
jtag
- verilog jtag源码及原理，还有debug模块。边界扫描等-verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.
pal_vedio
- 基于FPGA的pal制模拟视频显示程序，verilog Hdl-pal-d vedio display fpga verilog
ad_test
- ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现-ad9777 test procedures, the SPI is initialized, the use of ISE environment, the successful realization of comprehensive and
spi_controller
- SPI控制器，基于VERILOG描述，分模块设计，共6个模块，时钟产生模块，移位模块，主模块，从模块，定义模块，顶层模块。-SPI controller, based on the VERILOG descr iption, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top modul
xlx_s6_lx150t_dev-sch-revc032510
- avnet Spartan-6开发板原理图-avnet Spartan-6 development board schematics
FPGA-VIDEO
- FPGA图像采集程序，cmos图像采集、I2C控制、VGA图像像是模块-FPGA VIDEO