资源列表
video_stream_scaler
- 该模块能对视频分辨实时缩放，采用最近邻域和双线性差值算法。该模块可以实时配置输入输出的分辨率、缩放因子，缩放算法类型等参数，也可在编译时采用默认配置。-The Video Stream Scaler (streamScaler) performs resizing of video streams in a low latency manner, resizing with either bilinear or nearest-neighbor modes.The core offers run
AD9957_Signal_Generate
- AD9957芯片通过FPGA配置的verilog程序,要自建工程，代码测试完全可用-AD9957 chip FPGA configuration verilog program, to be self-built project, code test is completely available
tse_datapath_reference_design
- altera FPGA实现千兆以太网数据通信的程序源代码-altera FPGA Gigabit Ethernet data communication program source code
QPSK_T
- QPSK解调器的FPGA实现，VERILOG源码-FPGA implementation of QPSK demodulator，VERILOG source
fib
- 一个基于VHDL编程的可用于FPGA实现的斐波那契数列计算器- implemented a circuit in VHDL that calculates Fibonacci numbers
FPGA控制的红外循迹小车
- FPGA控制的红外循迹小车八个传感器利用PWM进行控制转弯和前进后退可以自启动
fpga_nes-master
- 这是一个完整的红白机nes游戏fpga实现，经测试可用，使用ise14.1以上版本的工程文件，开发板使用的是xilinx spartan6-This is a complete NES nes games fpga implementation, the test is available, use ise14.1 above version of the project file, the development board using xilinx spartan6
Altera_QuartusII_13.0_Windows_Crack
- quartus 13.0 的破解文件 最新版本的破解文件-quartus 13.0 crack file latest version of the crack file
(15-7-2)BCH
- Verilog HDL 语言编写的（15，7,2）BCH编码和译码功能-Verilog HDL language (15,7,2) BCH encoding and decoding functions
QPSK_DSSS
- 该程序使用verilog语言，编写了QPSK-DSSS系统的发端，主要模块包括对同相分量和正交分量的扩频，通过根升余弦滤波器，以及与载波相乘等模块。-The program uses the verilog language, written QPSK-DSSS system, the originator, the main modules include in-phase and quadrature components of the spectrum, through the root
Hx711
- hx711的数据读取程序，已测试完成，能正常使用-hx711 data reading program, has been testing is complete, the normal use
line_four
- 利用verilog HDL逐点比较法实现直线和圆弧插补-Use verilog HDL by-point comparison method to achieve linear and circular interpolation