资源列表
verilog
- Velilog大学教程PPT的PDF版本(The PDF version of the Velilog University tutorial PPT)
CAN总线，I2C，USB等的FPGA实现源码
- 控制器局域网总线协议的Verilog代码(The Verilog code of the CAN bus protocol)
wuziqi
- verilog HDL语言编写的五子棋算法的实现，可直接在Quartus中仿真。(The implementation of the Gobang algorithm written in verilog HDL language can be directly simulated in Quartus.)
等精度频率计
- 基于FPGA的等精度频率计，包括工程，doc和一些查找资料(An equal precision frequency meter based on FPGA, including engineering, Doc, and some lookup data)
nco1mhz
- 使用FPGA元件中的NCO产生1MHZ频率\相位可调的输出(Use the NCO in the FPGA element to produce 1MHZ frequency \ phase adjustable output)
led_test
- 基于Verilog硬件语言的流水灯设计，可以实现4个led灯按照流水灯的形式闪亮。(ased on the flow lamp design of Verilog hardware language, 4 LED lights can be realized in the form of flowing light.)
buffer
- Hi iam Ramana a research scholar,doing my phd from sathyabama university. Title: Designa video codec h.264 processor using verilog hdl. i request you to send video codec H.264 on Verilog hdl. regards D Ramana, M.Tech(Ph.D) SATHYABAMA
Two_Level_SVPWM
- 代码为两电平SVPWM调制算法的Verilog程序。包括扇区划分、时间计算、死区控制等。(The code is the Verilog program of the two level SVPWM algorithm. It includes sector division, vecter calculation, dead zone control and so on.)
deadzone
- 代码功能是实现脉冲信号的死区控制。根据输入脉冲实现10us的死区，避免IGBT直通。(The code function is to realize the dead zone control of the pulse signal. The dead zone of 10us is realized according to the input pulse, and the direct connection of IGBT is avoided.)
pipe25_rc5
- pipe可以用于绘制随机petri网和系统性能分析(pipe for help leaner in start stage get more about how to conduct petri net)
i2c_ctr
- 标准iic通信协议，项目中已经使用过，下载可直接上项目(The standard IIC communication protocol has been used in the project. On the basis of IIC, the configuration and detection function of the register can be added.)
device_dri
- 该程序结合iic驱动程序，可用自动检测硬件的寄存器配置参数是否正确，项目中已使用过(With the IIC driver, the program can automatically detect whether the hardware's register configuration parameters are correct. The program has been used in the project.)