资源列表
uart_design
- UART设计的VERILOG代码，具有FIFO功能，能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
piccolo_verilog
- 采用verilog设计的一个piccolo密码算法的硬件实现(Hardware implementation of a piccolo cryptographic algorithm designed by Verilog)
x264
- hwaccel = get_hwaccel
subtraction floating point
- subtract two number floating point (32 bit)
dayashankar_nair_verilog_2.1.tar
- finitie strate machine
dayashankar_nair_verilog_2.2.tar
- finite state machine
dayashankar_nair_verilog_1.3.tar
- verilog assignments one
DATA_Interleaver
- 这是交织的实现源码 可用于具体的工程实践(This is the interwoven implementation source code that can be used in specific engineering practices)
Verilog的135个经典设计实例
- Verilog HDL的13个经典实例。经过验证，值得学习(The 13 Verilog HDL classic examples. After verification, worth learning)
Verilog典型电路设计_华为
- Verilog典型电路设计,学习价值较高。(Verilog typical circuit design, learning value is higher.)
verilog黄金参考指南中文版
- Verilog设计典型指导资料,学习价值较高。(Verilog design typical guidance information, learning value is higher.)
Verilog-基本语法
- Verilog设计典型指导资料,有学习的价值(Verilog design typical guidance information, has the value of learning)