资源列表
uart_model_verilog
- uart通信协议的设计参考，对于初学者可以以此为参考进行设计，代码可在仿真软件中验证（modelsim、VCS等）。-Uart communication protocol design reference for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
usb_host_device_verilog
- USB-host-device控制模块的设计参考，对于初学者可以以此为参考进行设计，代码可在仿真软件中验证（modelsim、VCS等）。-USB-host-device control module design reference for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
SPI_SD_CARD
- 使用sopc系统，结合nios软件，实现sd卡的读写，学习FPGA编写的过程-Use sopc system, combined with nios software, sd card reader, prepared by the process of learning FPGA
B3LabGuide
- xilinx 的FPGA开发板的相关资料，可以很好地熟悉掌握开发板的使用，加快开发进度-Xilinx FPGA development board information, is a good way to master the use of the development board, speed up the development pro
practica1
- Se trata de compuertas analógicas de and y or
CIC_filter
- 抽取:(接收端) 中频信号IF 20M(采样率是50M) 下变频信号 MIX_O 1M(50M) 采用CIC滤波器进行降采样率。 插值:(发送端) 基带信号上变频到1M，采样率是2.5M，采用CIC滤波器进行升采样率处理。 注释：升采样率或者降采样率不会改变原始信号的中心频率，但是频谱分布会发生改变。-Extraction: (receiver) IF signal 20M (sampling rate is 50M) down-conversion signal M
Xilinx_I2C
- Xilinx FPGA的I2C Master例子-Xilinx examples of I2C Master
USB_SoftLock
- USB SoftLock, 包含VHDL for Xilinx FPGA，上位机驱动以及应用程序-USB SoftLock, Include VHDL for Xilinx FPGA, PC Driver and App
LCD-IP-CORE
- LCD Controller IP for Xilinx FPGA
USB_ulper
- USB ulper Link Layer design, role of Host and Device
zhonghuanAGVpro
- 采用ALTERA FPGA，nios ii内核的AGV控制程序，里面包含了PID算法及相关AGV控制逻辑-Using ALTERA FPGA, nios ii kernel AGV control program, which includes a PID algorithm and control logic associated AGV
sd
- 实现SD卡初始化以及读相关操作，包括项层、读模块和初始化模块- SD card to achieve read and write operations