资源列表
VGAController
- Easy VGAController in vhdl
8a
- 2 Flip Flops in VHDL
soma_loka
- Sum make in vhdl code
rs_232
- Comunication rs232 in vhdl
equalizer
- This the code for the channel equalizer and the test bench for this in the verilog code.-This is the code for the channel equalizer and the test bench for this in the verilog code.
convolution
- This the code for the convolutional and the test bench for this in the verilog code.-This is the code for the convolutional and the test bench for this in the verilog code.
demapperSharp1(16QAM)
- This the code for the demapper in the verilog code.-This is the code for the demapper in the verilog code.
inter_deleaver
- This the code for the interleaver and the deinterleaver in the verilog code.-This is the code for the interleaver and the deinterleaver in the verilog code.
mapperSharp1(16QAM)
- This the code for the mapper in the verilog code.-This is the code for the mapper in the verilog code.
mt9d112_ddr2
- 镁光MT9基于FPGA图像采集模块，该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete timing and interface, ddr2 memory
HDMI_4AV
- 该源码为基于FPGA的HDMI显示的一拖四的AV视频采集。该模块可方便移植在需要使用HDMI高清显示的场合，并且可将VGA显示一分为四，方便各个窗口显示不同的图像信息-The source for the FPGA-based HDMI display of a four of the AV video capture. The module can be easily transplanted in the need to use the HDMI high-definition displa
RD1213_Video_Pipeline
- This document describes the structure and implementation of a video pipeline demo design running in the Lattice ECP3-150EA-8FN1156C device based on the Sparrowhawk FX Board. This demo takes two of the four video streams DVI and SDI inputs and the