资源列表
safe_state_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
FTChipID_LV7.zip
- FTChipID_LV7.zip
OV7670_VGA
- 实现OV7670照相机采集和在VGA显示屏上进行显示，易于理解和学习。-OV7670 camera acquisition and display on VGA display screen, easy to understand and learn.
dac_ctl
- 主要功能为控制DAC芯片，来控制压控晶体振荡器，产生所需的时钟信号。-Mainly used for DAC control VCO to generate the required clock signal can be used directly.
simwindfarm-v1.0
- GFH GFH DFHFDHD GHDHFDHHFD DFHFDHDF-GFHGFHGFH DFHFDHD GHDHFDHHFD DFHFDHDF
pwm
- VHDL, quartet 2 , FPGA, cyclone II, controllen PWM brightness
chuanxing
- VHDL的串行通信程序,硬件描述语言，使用xilinx ISE软件-VHDL serial communication program
simplever
- this simple code to understand and, or and top level-this is simple code to understand and, or and top level
Combinational
- this is a sample of combinational circuit in Verilog and VHDL. such as multiplexer, decoder, adder etc
sequential
- this a sample of sequential circuit in verilog and VHDL-this is a sample of sequential circuit in verilog and VHDL
Filterfgfftd
- LIBRARY ieee USE ieee.std_logic_1164.ALL library work use work.fft_pkg.all
zongbian4
- 基于verilog语言的差分曼彻斯特编码，内包含数据的采集，CRC校验（8位），和编码，输出。附有完整的工程文件。可直接调用modelsim仿真。-Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be call