资源列表
verilog
- basic verilog codings in fpga
Design-and-Implementation-of-BIST-Using-Verilog.z
- BIST desing using verilog
jtag_latest.tar
- JTAG for veriolog-FPGA
uart2bus_testbench_latest.tar
- UART for benchmark circuit
Segmentation-4G
- Segmentation of the 4G standard
i2c_slave_fpga_verilog_code
- I2C的salve完整代码以及实现例子,使用verilog编写-The full implementation of I2C protocol by verilog
pin
- verilog 语言 编写。 实现洗衣机 的倒计时 显示。 以及各种洗衣模式的选择，芯片为ek10tc144-3-verilog language. Achieve washing machine countdown display. Laundry and selecting various modes, the chip is ek10tc144-3
AD0804_control
- 配置AD0804的VHDL代码，经过验证可参考学习-Configure AD0804 VHDL code, reference study validated
Control_AD9516
- 时钟芯片AD9516配置代码，VHDL开发，可仿真验证-Development, clock chip AD9516 configuration code, VHDL simulation
mealy_state_machine_v
- mealy状态机示例代码，可以在此代码上学期规范的状态机写法-mealy state machine sample code, this code can be on a state machine specification semester wording
moore_state_machine_v
- moor状态机的示例代码，再次基础上可以学习标准的状态机写法-moor state machine sample code, we can once again learning standards based on the wording of the state machine
user_encoded_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S