资源列表
multichannel-selector
- 本程序实现了二选一多路选择器的硬件功能，采用VHDL语言编写而成。-This program implements a second election multiplexer hardware function, written in VHDL language.
Serial-borrow-eight-subtracte
- 本程序实现了串行借位的八位减法器，采用VHDL语言实现。-This program implements eight serial borrow subtractor, using VHDL language.
Digital-clock
- 利用Quartus编程软件及EDA实验板（芯片为EP1C6Q240C8）完成数字钟设计，该数字钟有显示时、分和秒的功能。-When the Quartus programming software and EDA experiment board (chip EP1C6Q240C8) complete digital clock, digital clock showing the hours, minutes and seconds functions.
My-And
- And port made with nand gates in Verilog
Oc_spi
- FPGA的SPI接口例子，功能成熟，可以参考-SPI Master Core Specification
I2c_v13
- FPGA的I2C模块实例代码，有说明文档，值得参考啦-FPGA I2C Model Sample Code Docs
controller
- Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang Controller (control logic plus state register) VHDL FSM modeling- Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang C
memory
- Simple Microprocessor Design memory 256*16 8 bit address 16 bit data memory.vhd- Simple Microprocessor Design memory 256*16 8 bit address 16 bit data memory.vhd
DSP
- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001 VHDL Data-Flow modeling KEYWORD: generate, array, range, constant and subtype- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001
Controller(FSM)
- Simple Bridge (ESD book figure 2.14) by Weijun Zhang, 04/2001 RT level design using Controller(FSM) + DataPath- Simple Bridge (ESD book figure 2.14) by Weijun Zhang, 04/2001 RT level design using Controller(FSM) + DataPath
GCD-CALCULATOR
- GCD CALCULATOR (ESD book figure 2.11) Weijun Zhang, 04/2001 we can put all the components in one document(gcd2.vhd) or put them in separate files this is the example of RT level modeling (FSM + DataPath) the code is synthesize
Verilog_HDL_FPGA_washing
- 基于Verilog_HDL的FPGA程序(智能洗衣机) 以DE0板为开发工具-The FPGA-based Verilog_HDL program (smart washing machines) for the development of tools to DE0 board