资源列表
brent_kung_add
- BRENT KUNG ADDER CODE
Adder-Designs-using-Reversible-Logic-Gates
- REVERSIBLE LOGIC BASED ADDERS DOCUMENTATION
FPGA_phase-shift
- 本文介绍基于FPGA和DDFS技术，应用Altera公司的FPGA开发工具DSP Builder设计数字移相信号发生器，该数字移相信号发生器的频率、相位、幅度均可预置，分辨率高，精确可调。-This paper introduces FPGA and DDFS technology based on FPGA development tools DSP Builder design of digital phase shift signal generator using Altera, fre
cpld
- 使用cpld完成多个串口切换通信，能够完成快速通信，已经完成验证-Using CPLD to complete multiple serial communication
XuLie
- 序列检测机，可检测8位数字序列，米勒型状态机-Sequence detector can detect 8-digit sequence, Miller-type state machine
piccolo
- piccolo 密码算法的Verilog实现-piccolo algorithm
mux21
- 二选一选择器的Verilog的实现。二输入，一片选段。-realization of mux21
mux31
- 三选一选择器的Verilog实现。三个输入端，一个片选端。-realization of mux31 using verilog.
seller_moore
- 用Verilog实现十六进制计数器。内含有整个完整工程。包括tb文件。-realiaztion of timer16 using verilog
timer16
- 十六进制计数器的的Verilog实现。内有整个工程，包括tb文件。仿真可通过-realizaiton of timer16
uart_rx
- 串口接收模块代码，根据设定的串口波特率，可以正确接收串口的数据-Serial receive module code, according to the set baud rate, serial data can be correctly received
practica1
- tester.vhd library IEEE use IEEE.STD_LOGIC_1164.all use IEEE.STD_LOGIC_ARITH.all use IEEE.STD_LOGIC_UNSIGNED.all LIBRARY lpm USE lpm.lpm_components.ALL entity practica1 is port ( RESET : in std_logic clk :