资源列表
counter
- FPGA编程，用Verilog语言实现4位累加器功能-The FPGA programming, realize four accumulator with Verilog language features
taxi
- FPGA编程，用Verilog语言实现出租车计费器功能-The FPGA programming, the taxi is realized with Verilog language features
xuljc
- FPGA编程，用Verilog语言实现序列检测功能-The FPGA programming, using Verilog language implementation sequence detection
MUX_VHDL
- A multiplexer allows digital signals several sources to be routed onto a single bus or line. A input to the multiplexer allows the source of the signal to be chosen. We look at two multiplexer examples in this tutorial, the first multiplexes two
VGA
- VGA 640*480 controlling and blanking signal in Verilog HDL .
tlv5638_ise12migration
- 使用SPI通信协议，quartusII开发环境，编写5638驱动-Using SPI communication protocol, quartusII development environment, the preparation of 5638 drivers
tb_contrast_stretch
- contrast strech for image pixles
log_generator
- log10 generator in vhdl. simulated in Modelsim
wdog_sp805
- 看门狗模块是一个AMBA从属模块连接到高级 外设总线（APB）。看门狗模块包括一个32位的递减计数器用 可编程超时间隔具有产生中断和能力 对超时复位信号。它的目的是要使用到复位应用于在一个系统 事件的软件故障。-The Watchdog module is an AMBA slave module and connects to the Advanced Peripheral Bus (APB). The Watchdog module consists of a 32-b
calculator
- 能够实现8位的无符号数的乘除法，模拟了笔算的过程-Unsigned 8-bit multiplication and division can be achieved, simulation the written calculation process
lcd_system
- lcd系统：包含了图片显示、汉字字库、PS2输出的lcd显示系统。-lcd system: Contains pictures show, Chinese character, lcd PS2 output display system.
FIFO
- FIFO先进先出，控制时序，对urat、SDRAM、DAC等时序理解都有帮助-FIFO FIFO control the timing of urat, SDRAM, DAC and other timing understanding have helped