资源列表
DM9000A
- DM9000A 链接FPGA接口设计及NIOS驱动-DM9000A FPGA interface for NIOS timescope
pulse
- 一个产生可调频率和可调占空比Verilog源代码，希望对你起到作用-A variable frequency and variable duty cycle generates Verilog source code, you want to play a role
time60
- 一个占用资源很少的时钟产生Verilog代码，值得借鉴-A small footprint clock generator Verilog code, is worth learning
LCDandSDRAM-test
- 一个SOPC实验，关于LCD的控制和SDRAM的使用方法-A SOPC experiment on LCD of control and the use of SDRAM
MC8051_test
- 基于SOPC的MCU51单片机内核的开发，需要使用51单片机内核的直接拿走。-MCU51 microcontroller core based SOPC development, requires the use of 51 microcontroller core directly away.
MicroC-OSII-sopc
- MicroC-OSII 在SOPC环境下的搭建，程序已经搭建好一个Micro-OSII开发环境-MicroC-OSII built in SOPC environment, the program has set up a Micro-OSII good development environment
DE0_developboard_VGA
- DE0开发板VGA接口显示硬件实现，可显示图片。-DE0 board VGA interface to display hardware, display pictures.
IIR_TEST
- fpga开发IIR滤波器，滤除声音中的噪声。-fpga development IIR filter, filter out the sound of the noise.
uart_txrx
- fpga 串口发送与接收VHDL硬件语言实现。附有仿真测试程序。-fpga serial port to send and receive VHDL hardware language. With simulation testing program.
traffic
- FPGA编程，用Verilog语言实现交通灯功能-The FPGA programming, implement traffic lights with Verilog language function
Source
- This power point file consist of a lot of different vhdl code for component with source code VHDL (VHSIC Hardware Descr iption Language) is a hardware descr iption language used in electronic design automation to describe digital and mixed-signa
clock
- FPGA编程，用Verilog语言实现数字钟功能-The FPGA programming, the function for digital clock with Verilog language