资源列表
emif
- 异步EMIF接口，16bit，FPGA程序。-asynchronous emif，16bit，FPGA program
shuzishizhong
- 基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能-DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board
AES
- AES的加密解密verilog全部源代码-AES encryption and decryption verilog full source code
jingsai
- 微机原理课程实验应用，竞赛抢答器的设计，文本档-Microcomputer Principle Course Laboratory applications, Contest Responder design, text files
Cordic
- block-matching 3D filtering (BM3D) [2], and low-rank regularization [3], single-image based denoising performance has greatly improved, with image details well recovered when the image is slightly noisy. However, with the increase of noise le
Turbo_ECC
- However, since they use general priors for all kinds of noisy images, without considering the content of the noisy image, they soon reach their performance limitation (comparable to BM3D) and tend to introduce artifacts if the noisy image doe
YCbCr2RGB
- YCbCr turn RGB module, to apply to the project.
test-led
- 流水灯程序，利用了VHDL，虽然程序比较简短，但是，用的还是比较经典的-Light water program, the use of VHDL, although the procedure is relatively short, but with quite classic
7210040034_Yasifa-Rakhma_ProjectAkhir
- REPORT OF Embedded System VHDL 3-to-8 Decoder using a For-Loop
SD_Card
- sdhc卡spi扇区读verilog例程。包含sdhc卡初始化模块及一个扇区读模块，扇区读完数据放在一个fifo中缓存，为之后的工作做准备，可以集成到自己的项目中。已经在闪迪8Gsdhc卡上亲测成功-sdhc card sector read spi verilog routine. Initialization module and a read module contains sdhc card sector, the sector read data in a cache fifo in
verilog
- verilog的基础入门资料，很适合初学者学习参考-verilog basis for introductory information, it is suitable for beginners to learn reference
stopwatch_if
- 用IF语句实现秒表功能的代码，显示范围在000至9-Stopwatch function code with the IF statement, displayed in the range of 000 to 99.9.