资源列表
proyecto-I2C
- It s a VERILOG code to initiate a I2C protocol on an FPGA and an EEPROM of 512 KB
dds_cordic
- 这是我自己编的一个基于流水线结构CORDIC算法实现DDS，32位的频率控制字的输入，CORDIC算法的迭代次数为15次。-This is my own DDS based on series of the pipelined CORDIC algorithm， a frequency control word：32 bit .The number of CORDIC iterations for the 15 time。
TLC1650
- TLC1650驱动程序 Verilog HDL-TLC1650driver Verilog HDL
ML605_RX_H264
- H.264视频压缩硬件语言，基于ＦＰＧＡ的设计语言。非常棒的语言设计-Solution of H.264 video compression hardware design language, based on FPGA language
dianzhen
- 基于FPGA的点阵模块，输入汉字信息后可以逐行扫描-After the dot-based FPGA module, input Chinese information can be progressive scan
dianyuan
- 实现按键控制AD三通道的电源转换的功能。-AD three buttons control channel to achieve power conversion
TLC1620
- 基于FPGA的Verilog语言实现的六十进制计数器-FPGA-based Verilog language implementation of six decimal counter
tx_module
- 串口通信，实现开发板与计算机之间的数据传输-A serial port communication, realizing the development board and the transfer of data between computers
vga_driver
- 基于EP3C16的VGA显示驱动工程。时钟40M，图片存储在FPGA内部的ROM中，VGA显示器分辨力为800*600*60Hz，存储图片需要800*600点（bit），由于EP3C16的ROM不够大，ROM中存储内容为8bit*30000；显示器内容为上下半屏分别显示ROM中的内容，显示图片相同。ROM中的内容由地址线的变化来控制。-Display driver works based EP3C16 of VGA. Clock 40M, pictures stored in the ROM o
IDEA
- IDEA算法硬件实现，可以在ise系统上实现-IDEA algorithm implementation
hpi
- 用CPLD实现4个C6201通过HPI接口互连的逻辑设计，包含VHDL程序-4 of C6201s through the HPI interface logic design of interconnection with CPLD, including the VHDL program
shuzizhong
- 基于VHDL语言的数字钟，有元件例化，修改时钟功能 Quartus II平台-VHDL language based digital clock, there are component instantiation, modify clock function Quartus II platform