资源列表
verilog_receiver
- 标准的verilog rs232 接收功能通讯源码，测试可用，已经在实际系统开发中使用。-Standard verilog rs232 reception communications source, testing is available, have been used in the actual system development.
A201001-2186
- 频谱分析仪是信号处理研究领域必不可少的工具。现有的基于快速傅利叶变换的频 谱分析仪能对线性的平稳的信号进行有效分析，但难以分析出非线性非平稳信号的瞬时频率 能量变化情况。针对此问题，本文设计了基于希尔伯特黄变换的频谱分析仪，能够对非平稳 信号进行有效分析。所设计系统以DE2-FPGA开发板为硬件平台，结合了NiosII的软核处 理器加以实现，可对采集的外部信号进行希尔伯特黄变换，得到信号的时间-频率-能量三维 谱，并可在VGA上实时显示出来。系统测试结果表明，所设计频谱分析仪
wavelet
- 根据小波去噪的原理及特点，提出了用FPGA实现小波实时信号处理的方法。实验结果证明采用FPGA实现小波信号处理能在低信噪比的情况下有效去除噪声，同时能够满足信号处理系统的实时性要求。-According to the principles and characteristics of wavelet denoising, a method using wavelet FPGA real-time signal processing. Experimental results show that
counter_vhd
- An asynchronous (ripple) counter is a single d-type flip-flop, with its J (data) input fed its own inverted output. This circuit can store one bit, and hence can count zero to one before it overflows (starts over 0). This counter will increment once
counter_vhd
- Counter is used to count the value of the memory register in the digital circuits-Counter is used to count the value of the memory register in the digital circuits....
counter_14uou
- Counter wikipediya information will help you to understand about this program-Counter wikipediya information will help you to understand about this program
sw_xiaodou
- 基于verilog的按键消抖控制led程序-Based verilog button debounce control led program
FIFO
- Nios ii fifo,用于MCU通过nios ii进行fifo通信,verilog格式.-Nios ii fifo, for MCU FIFO communication, through the Nios II Verilog format.
trafficlights
- Verilog实现的交通灯功能工程 在Quartus环境-traffic lights of Verilog
code
- this code for assessment
the-basic-presentation-of-VerilogHDL
- VerilogHDL扫盲文介绍Verilog的基础知识-the basic presentation of VerilogHDL
AXI_VIP
- axi vip code used in almost all the interface projects in the soc and verification environments in arm processors