资源列表
COMB
- We use port map statement to achieve the structural model (components instantiations). The following example shows how to write the program to incorporate multiple components in the design of a more complex circuit. In order to simulate the design, a
CALIBRATION
- Calibration is a comparison between measurements – one of known magnitude or correctness made or set with one device and another measurement made in as similar a way as possible with a second device. The device with the known or assigned correctness
all-code-files
- code for virus detection processor in vhdl
finalcode
- vhdl code for simple virus detection processor. it can also develop in verilog
d-Flip-Flop
- D flip flop and some other codes added together recomended use is adding layer not use in a single bench
mux8to1_with_if
- this code to input 8 different data and make them out sequentialy -this code to input 8 different data and make them out sequentialy
Projects
- this is sub and adder in vhdl &writed in ISE
verilog-mode
- verilog mode for gvim
UVM_Guidlines
- UVM Coding Guidelines for verification
Verilog code about a VGA based ball and gun game
- This code can be performed directly on the SPARTAN-3A FPGA board as long as a VGA port is connected to this board. After initialization, a ball and gun will appear on the screen and you can control them and playing the game by using the button from t
Array-multiplier
- Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
pid
- pid controller design based vhdl code in xilinx code-pid controller design based vhdl code in xilinx code.....................