资源列表
d_ff_cout_tb
- D FLIP FLOP TEST BENCH
qpsk_mod
- QPSK modulation using vhdl programming ..i hope it ll be useful-QPSK modulation using vhdl programming ..i hope it ll be useful...
VHDL
- VHDL，介绍简单的语句，有计时器、频率计等例子。-Very-High-Speed Integrated Circuit Hardware Descr iption Language
draw_char_type
- FPGA字符显示控制，RAM作为显存地址存放现在内容，ROM作为显示字模。-FPGA character display control, RAM memory address is stored as the content now, ROM as a display font.
video_form_convert
- 将ADV7181解码出来的数字视频，提取亮度信号作为视频输出。-The ADV7181 decoded digital video, the luminance signal is extracted as a video output.
video_shape_center
- FPGA将二值化的视频提取目标的位置信息，最终计算出目标的型心。-FPGA binarized video extract location information of the target, the final calculation of the target core.
dsp_link_tx16
- FPGA到TS201的link_port接口，以16位的数据格式传输到DSP。-FPGA to TS201 s link_port interface, 16-bit data format for transmission to the DSP.
DSCH2
- VLSI compiler or nano chip designer.
lec_Chap2
- Verilog Hardware Descr iptive Language
source
- VHDL Altera example code
phase-locked-loop-implementation
- 在FM0数据解码时，利用锁相环生成数据同步时钟信号。文件为锁相环实现。Verilog HDL-When FM0 decoding data using the phase-locked loop generates the data synchronizing clock signal. File for phase-locked loop implementation.Verilog HDL
decode
- 通信数据中FM0数据的解码接收，解码数据和输出同步时钟。Verilog HDL-FM0 decoding the received data in the communication data, the decoded data and outputs sync clock。Verilog HDL