资源列表
spartan5
- vhdl program for adc of spsrtan 3e
netlist
- vhdl program of matlab file converted to vhdl
netlist8
- vhdl program of matlab file converted to vhdl
netlist2
- vhdl program of matlab file converted to vhdl
exa1
- 8位全加器，为EDA的第一个实验，由半加器和或门组成-8 full adder bit EDA experiment first simple experiment, through the OR gate constructed with half-adder
exa1_adder
- 之前上传的是全加器，这个是自己设计的8位全加器，8位并行全加器-Before uploading the full adder, this is their own design eight full adders, eight parallel full adder
02_run_flash_led
- 利用黑金开发板AX301开发的第一个实验，流水灯，适用于初学者，调试通过-Black Gold AX301 use development board developed the first experiment, water lights, suitable for beginners, debugging through
fixed_pointDivider
- 关于定点除法的VHD实现,找了好久，奉献出来大家一起学习！-fixed_point divider is implemented in FPGA .
piso_beha_tb
- parllel toserial out test bench
priorityencodtest
- parity encoder test bench
mod_n_counter_tb
- MODULO N COUNTER VHDL
johnson_count_tb
- JHONSON COUNTER TEST BENCH