资源列表
uart_verilog
- 232串口Verilog语言实现，可供新手参考编写，不太完善，需做补充。-Uart 232 Verilog
proje-vhdl
- ASYMMETRIC LARGE SIZE MULTIPLIERS WITH OPTIMISED FPGA RESOURCE UTILISATION
multiplier
- Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support
vga
- 一个简单的VGA小应用，实现功能是一个红色小方块，可以在屏幕上沿任意方向移动，如果碰到屏幕边缘，可以反弹回去。-A very easy VGA test case
microzed_tft
- TFT on microzed vhdl source code
zynq-xdma
- zynq xdma source code
axi_dispctrl
- zynq AXI display controller source for zybo
DE2_115_PS2_DEMO
- 完成确定鼠标目前的位置X,Y轴，以及对鼠标三键的检测。-Completion determination mouse current position X, Y-axis, and detection of mouse triple bond.
UG586-7SeriesDMIUserGuide
- UG586 - Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )-UG586- Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )
manchester_encoder
- 曼切斯特码解码器verilog程序，已通过ModelSIM仿真，可用-Chester Verilog decoder procedures, has been through the ModelSIM simulation, the available
x16_to_boc32
- 16位串行数据转32位并行数据Verilog程序，已通过仿真，可用-The 16 bit serial data to 32 bit parallel data Verilog procedures, has been through the simulation, the available
a_vhd_16550_uart_latest.tar
- 串口程序，基于16550内核，有不同的版本，比较齐全。-the UART program，based on 16550 core，have several versions。