资源列表
DE2_LED_sm
- 驱动DE2—70开发板上数码管，并设计了一个时钟计数器，时钟计数时，分，秒。-DE2 70 development board driver digital tube, and designed a clock counter, clock count, minutes, seconds.
CY7C68013andFPGAinterface
- CY7C68013与FPGA接口的Verilog HDL实现-Verilog HDL CY7C68013 and FPGA implementation of the interface
timer.tar
- this a 32-bit general purpose timer.-one time mode continue mode
filter
- 滤波器源码，实验室搭电路的必备源码，很好用-Filter source code, circuit lab take the necessary source code, very easy to use
filter_tb
- 滤波器测试代码实验室搭电路的必备源码，很好用-Laboratory test code circuit filter take the necessary source code, very easy to use
module-mf
- verilog Implementation of Mean filter to implement in FPGA
sleep_wake-up
- SLEEP WAKE UP FOR CSR CPU
e2prom_w_r
- FPGA的 EEPROM 读写测试代码， 包括源代码和测试代码-test bench of EEPROM write and read for FPGA
i2cslave_verilog
- 自己实现的一个i2c slave, 已经用在自己的工程里。好用！-I2C slave.
relay_test
- Simple relay trigger
DE4_230_DDR2_UniPHY_QSYS
- DE4系列开发板关于ddr2在Qsys系统搭建的实例，有一定参考价值，。-DE4 series development board on the DDR2 in the example of Qsys system, has a certain reference value,.
bcd27seg
- Tranfer BCD to 7 Segs