资源列表
bishe3
- 以复杂可编程逻辑器件(CPLD)为核心的新型通用数字触发器-Based on complex programmable logic device (CPLD) as the core of the new universal digital trigger
verilog-led
- 此程序是Verilog语言编写的一个流水灯程序，简单易行-This program is written in Verilog language a light water program, simple and feasible
PIPELINE
- （包含详细说明文档和简单汇编转机器码翻译器）五级流水线实现MIPS指令集（30条）含异常处理。结构采用多分支预测结构（基于历史的动态分支预测）-(Contains detailed documentation and compilation turn simple machine code translator) five pipelined MIPS instruction set (30) with exception handling. Structure using multi-bran
uart_top
- FPGA verilog hdl UART232 工程及相关源程序，可直接使用-FPGA verilog hdl UART232 project and source code use it directly
top_hwx
- quartus 红外遥控接收解码工程以及相关代码。可直接使用-quartus ii hwx project and source code 毛can be directly used
CacheFromScratchFinalWeek_ise12migration
- VHDL implementation of an 8-bit multilevel cache. Produces timing diagrams when run on a suitable IDE such as Xilinx.
VGA
- quartus ii verilog hdl 实现VGA时序及显示的工程和源程序 -quartus ii verilog hdl vga timing project and source code
PCF8563
- quartus ii 实时时钟pcf8563工程及源码 Verilog hdl 实现iic总线-quartusii realtime pcf8563 project and code and IIC verilog hdl
I2C_contrl_LED
- I2C的top文件，是按照标准的I2C协议编写的，已通过调试，放心使用-I2C s top document is written in accordance with standard I2C protocol has been through debugging, ease of use
sync_fifo
- 同步fifo实现代码，包括的参数：数据宽度、fifo深度、地址宽度；状态信息包括：full, empty。-verilog RTL code which implement a synchronous FIFO function with data width, fifo depth, address pointer width parameterized.
license_ISE_11_to_12_AVNET-yyy
- ise11.1的license，包括了fifo等IP核，谢谢大家的光顾。-ise11.1‘s license which provided some ip like fifo.
top
- FPGA开发UART软件有一定的参考价值，请参考该软件进行编译Altera软件编写的-FPGA development software UART has some reference value, refer to the software to compile software written Altera