资源列表
Day-3-Training-Material
- OneSpin培训资料 OneSpin广泛用于芯片设计的断言验证。-OneSpin training material can help user understand how to do assertion verification in ASIC design.
cb_convert
- 把串行输入转换为并行输出或并行输入转换为串行输出的过程。能将串行接收到的’1’或’0’字符，每8位按顺序（先接收到的处于低位）排列为一个8位宽的字节输出。为保证数据传输中无误，同时发出一位奇校验位。-The serial input into parallel output to serial or parallel input output process. Capable of serial received a 1 or 0 character, every 8 sequentia
filter2
- 本实验完成加权均值滤波，其原理如下： 设采集到的数据按节拍输入，依次表示为d0，d1，d2，d3，d4,…，则输出依次为 do= d0*1/4+d1*1/2+d2*1/4 do= d1*1/4+d2*1/2+d3*1/4 … 假设采集到的数据为8位unsigned，输出do只保留整数。-This experiment is completed weighted mean filter, which works as follows: Set data collected
wendu_convert
- 完成一个摄氏温度（的整数）转化为华氏温度的电路，关系如下： F＝C*9/5+32-A Celsius temperature to complete the (integer) into circuit Fahrenheit, relations are as follows: F = C*9/5+32
chengfaqi
- 完成该3位3位的乘法器,把乘法问题转化为逻辑“与”运算和加法运算。-The completion of the 3 3 bit multipliers, the multiplication problem is transformed into a logic and operation and the addition operation.
c5c
- 实现5人表决的功能，并有倒计时跟指示功能。-Implement 5 people vote, and the timing and voting results show.
jiafaqi
- 本实验中，我们将设计一个能进行加运算的8位（包括符号位）运算电路-In this experiment, we will design a can add operation 8 (including the sign bit) arithmetic circuit
manchesteruart_latest.tar
- Manchester编码转uart的vhdl 代码-Manchester to uart
HDLC-Controller---Documentation
- hdlc 编解码 vhdl fpga 说明文档-hdlc encoder decoder vhdl
Digital-Transmission
- 数字量通讯教学文档，图形化解释，说明，Digital Transmission-Digital Transmission
FPGASHIYAN
- 含有多个FPGA实验，包含代码，都是可用的，蛮适合初学者的。-Contains a number of FPGA experiments, including code, are available, very suitable for beginners.
ParallelScrablerDescrambler
- VHDL code for parallel 6-bit scrambler and descrambler