资源列表
ldpc-code
- ldpc codes are low dencity paRity checking matrix to check the parity on matrix based g and h algorithm based on algorithm matrix input will be added to this code
ldpc-decoder-code
- Specify the decision method used for decoding as one of Hard decision | Soft decision . The default is Hard decision . When you set this property to Hard decision , the output is decoded bits of double or logical data type. When you set this property
UART
- （1）在FPGA上设计UART接收模块实现从PC接收串口数据(RS232串口通信)； （2）在FPGA上设计UART发送模块，把从PC接收的数据的16进制值加1再发送给PC； -(1) Design UART receiver module receives serial data (RS232 serial communication) the PC to the FPGA (2) Design UART transmit module on FPGA, the hexadecim
DDS
- 基于fpga的DDS详细设计方案 verilog语言 正弦计算器则对该相位值计算数字化正弦波幅度（芯片一般通过查表得到）。DDS芯片输出的一般是数字化的正弦波，因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。-Direct Digital Synthesizer base on fpga use verilog Sine calculator to calculate the value of the digital phase sine wave amplitu
mpi
- MPI接口就是CPU和逻辑之间通信的一个接口，一般使用总线方式，总线一般有两种标准，一种是MOTO模式，另外一种是intel模式。-MPI interface is an interface for communication between the CPU and the logic, the general way of using the bus, the bus generally have two standards, one is MOTO mode, the other one i
flow_proc
- FPGA FLOW verilog流水线把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。以芯片面积换取时间，即面积换取频率-FPGA FLOW verilog To a complex pipeline logic is divided into several blocks to achieve a relatively simple, reduce the logic level signal, increasing the frequency. The chip a
sclk_switch
- fpga verilog 在有些电路中需要时钟切换，比如某个电路支持高速模式和低速模式，在高速模式下系统工作在125M时钟，在低速模式下系统工作在3M时钟，在这样的设计中需要动态的将时钟从高频切换到低频，或者从低频切换到高频，切换过程可能会出现毛刺，是非常危险的，为了避免这个问题，有两种方法： 1、 在时钟切换时，进入复位，只有当切换完成时，复位才结束 2、 采用时钟切换电路。 -fpga verilog Need some clock switching circuit, such
DDS
- 任意波形发生器,可用按键，实现4种常见波形的转换-Arbitrary waveform generator, can be the key to achieve four kinds of common waveform conversion
UART_VHDL
- VHDL 实现 UART 全双工通讯，可以独立使能接收和发送，具有发送和接收完成标志位。-VHDL implementation of UART full duplex communication, can independently make can receive and transmit, with sending and receiving complete flag.
FPGA-based-display
- 基于FPGA的四位数字循环动态数码显示，内含100M分频器-FPGA-based digital loop two-digit display
dance-box
- 利用FPGA实现的跳舞机，有VGA的模块，二进制到BCD转换的模块等-Using FPGA to achieve Dance Dance Revolution, have VGA module binary to BCD conversion modules, etc.
taxi_THE-FINAL
- 基于FPGA的汽车计费系统，根据不同的情况会有不同的计费方式，基本能够符合实际情况-FPGA-based auto billing system, depending on the situation will be different billing methods, and can basically meet the actual situation