资源列表
mul16
- 16位二进制数移位乘法器的实现,使用Verilog HDL实现-The realization of the 16 bit binary number shifting multiplier, use Verilog HDL to implement
clock2
- 基于Verilog HDL及DE2开发板的数字钟设计，使用Verilog HDL实现-Based on Verilog HDL and DE2 development board of the digital clock design, use Verilog HDL to implement
HDB3-encoderauncoder
- HDB3编码器与解码器，以及RTL图，使用Verilog HDL实现-HDB3 encoder and decoder, and RTL diagram, use Verilog HDL to implement
ManchesterCode
- 改程序将实现对两个信号的曼切斯特编码，以用仿真软件验证过了-Reform program will achieve two Manchester encoded signal to a validated using simulation software
mo60xianshi
- 使用ISE软件在basys2开发板上写的模60计数器-Using ISE software development board wrote in basys2 counter mold 60
VHDLfre
- 四位十进制频率机，自动测频，锁存，清零功能-Four decimal frequency machines, automatic frequency measurement, latch, clear function
decoder38-ok-38
- 基于Quartus II软件实现38译码器功能。-Decoder function to achieve 38
music
- vhdl语言编写代码 梁祝音乐播放 fpga实现-vhdl code written fpga realize Butterfly music player
soda
- 实现一个苏打可乐售卖机，包括时钟分频，自动找零，能否售卖成功等功能。是中山大学移动信息工程学院数字设计的基础练习之一。-Achieve a Coke vending machine soda, including the clock divider, automatic change, the ability to sell successfully, and other functions. Exercise is one of the basic movement of Informatio
lab7_adders2
- 加法器的实现verilog SMIES实验课程-The implementation of adders. Experiment of SMIE.
lab7_adders3
- 加法器的verilog实现，第二种方法：超前进位加法器 -Another implementation of adder in verilog
lab7_2_new
- 移动信息工程学院实验课程源码：用FSM实现soda_machine(自动售货机)-Use verilog to implemwnt a soda_machine