资源列表
3-8-assign
- 此程序采用assign语句实现3-8译码器功能，仿真波形正确。-This program uses the assign statement to realize 3-8 decoder function, simulation waveform is right.
cordic16
- 16位cordic算法代码，可用于软件无线电理念下的数字接收机-the 16 bits cordic codes in VHDL
asyn_fifo
- verilog asyn_fifo,内含详细说明,同步FIFO为TPRAM-asyn_fifo include detailed instruction，Synchronous FIFO for TPRAM
TCAM
- 基于TCAM的高速路由查找，逻辑实现深度为32的内容查找，得到索引和命中指示-TCAM lookup based on a high-speed routing logic to realize the depth of content to find 32, get indexed and hit instructions
syn_fifo
- Verilog，syn_fifo ，内含详细说明，同步FIFO为TPRAM-Verilog, syn_fifo, containing detailed instructions for synchronous FIFO TPRAM
mux-demux-lab
- mux模块及demux模块实现，包括代码和相关讲解，可以参阅。-mux and demux model,including VHDL code and process
shifter1
- VHDL实现桶式循环移位器，经时序仿真测试正确，循环移位器-barrel cyclic shifter by vhdl
shifter2
- 改进型桶式循环移位器，用VHDL实现，经时序仿真测试正确-modified barrel cyclic shifter by vhdl
module_tft
- TFT 液晶屏显示，通过按键，显示不同的曲线-TFT LCD display
alu
- 16位微处理器，能完成算数移位，逻辑移位，数字比较，逻辑运算等功能-16-bit microprocessor, to complete arithmetic shift, logical shift, numeric comparison, logical operations and other functions
chuli
- 四个模块，用来完成数字比较，移位，逻辑运算，符号数加法等功能-Four modules, for performing digital compare, shift, logical operations, additions and other functions symbols
dlx_modules.v
- 经典dlx module文件，if和id模块做了部分修改-Classic dlx module file, if id module and made some modifications