资源列表
PS2_SOC2
- 利用Verilog HDL设计了PS2鼠标。 我们在Altera公司的Cyclone开发平台上测试了这个模块。正常动作，可以直接利用。-This is a state-machine driven serial-to-parallel and parallel-to-serial interface to the ps2 style mouse.
LIBRARY-IEEE
- 将1Mhz的频率信号转换成29hz的频率。分频器-Converting the frequency signal into a frequency of 29hz of 1Mhz. Divider
DDS
- dds测试程序，例化了DDS可以发出频率和相位可控的正弦波形-dds test program, for example, can issue of the DDS frequency and phase controlled sinusoidal
daima
- Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。 模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期
8bitsprocessor
- 8位RISC微处理器的设计与仿真，精简指令集-Design and Simulation of 8-bit RISC microprocessors, reduced instruction set
barrel-shifter-verilog
- this code is used for implementation of barrel shifter using verilog language
pararel-8-bit-adder-verilog
- implementation of 8bit adder with pararel computation. It s use S/P converter and P/S converter. The code is written in verilog language
serial-cordic-verilog
- implementation of cordic algorithm for many aplication like cos, sinus, polar to rectangular conversion and rectangular to polar conversion. It s written in verilog language and testbench is included
dds信号发生器
- dds正弦信号发生器源代码，适合处于学VHDL学生查阅
DDS
- 基于FPGA的数字信号合成器（DDS）,采用VHDL语言编写，能够实现正弦波、三角波、方波、锯齿波这四种波形的产生。 提示：最后输出的模块是串行DA，可根据具体情况更改驱动。-Digital synthesizer (DDS) based on FPGA, using VHDL language, to achieve sine wave, triangle wave, square wave, sawtooth waveform generation four. Tip: The la
CORDIC_IP
- 基于CORDIC实现正弦信号的仿真实验，通过使用自带的IP核CORDIC可实现正弦信号的产生。-Based on CORDIC achieve sinusoidal signal simulation by using built-in IP core CORDIC can achieve sinusoidal signal.
VGA
- VGA显示棋盘和条形图案。通过实验板上的按键的切换，可实现图形的切换，适合VGA的初学者。-VGA display board and a stripe pattern. Through experiments panel button switch, enabling graphics switching VGA for beginners.