资源列表
dds_
- 基于VHDL的DDS 串口控制 ROM 文件由MATLAB生成-dds using VHDL serial control
sv-reference-doc
- systemverilog入门 用于IC验证-for test
proda_FixPt
- Fixed point code of vector multiplication
pso2
- i want VHDL coding for doing my project-i want VHDL coding for doing my project..
pso3
- i want VHDL coding for doing my project
Virtex-6-Family-Overview
- Virtex-6 Family Overview
shifter
- 用vhdl语言采用时序电路(移位寄存器)的方式实现（7，4）循环码编码器-Vhdl language used by the timing circuit (shift register) way to achieve (7,4) cyclic code encoder
UART
- Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a s
SRAM
- DE2-35 SRAM简单读写VHDL源码，可以通过开发板上拨动开关输入数据，在LED上显示读写情况-DE2-35 SRAM to read and write simple VHDL source code, can input data through the development board to toggle switch, display to read and write in LED.
99mul_3
- 九九乘法表系统，ARH信号低电平时可手动输入乘数、被乘数；ARH高电平时自动生成乘数、被乘数进行99乘法计算。在自动过程中若ARH置0，则暂停当前自动生成的乘数、被乘数乘法运算，可进行外部输入，当ARH再次回到高电平1时，则返回暂停处的乘数、被乘数并继续向下运算。START信号具有一个复位重启的功能。-Nine nine multiplication table system, ARH signal in low level can be manually input multiplier, t
BitHound_SP601_1.0_
- 逻辑分析仪器代码，VHDL实现，支持100M采样速度-Logic analysis instrumentation code, VHDL implementation, support 100M sampling rate
VHDL
- 数字电路中常用的3线-8线译码器及8线-3线优先编码器的VHDL语言的功能描述-That is commonly used in digital circuit lines to 3-8 8 line to 3 line priority encoder decoder and the function of the VHDL language descr iption