资源列表
spatiotemporal_computing_core
- 用VHDL实现时空混沌：耦合映像格子(CML)-The spatiotemporal chaos of coupled tent map lattice implemented by VHDL.
5b6b-decode
- 5b6b decode,verilog代码，已验证。-5b6b decode, verilog code has been verified.
CMI-code
- cmi docer,verilog语言，已验证。-cmi docer, verilog language, has been verified.
cmi-decode
- cmi decoder,veilog代码，已验证-cmi decoder, veilog code has been verified
clander
- Verilog HDL编写的电子时钟 可以显示 时分秒 能够调整时间-Verilog HDL prepared using the electronic clock
ml40x_cpld
- xilinx ML40X开发板 的CPLD 例程-the cpld demo of xilinx ml40x
ml40x_usb
- xilinx ml40x 开发板的usb 例程-the usb demo of xilinx ml40x
ml401_2_3_schematics
- xilinx ml401/ml402/ml403 开发板原理图-the schematics of xilinx ml401/ml402/ml403
ml40x_vid_demo_v3.1_release
- xilinx ml40x demo 配置文件- the demo configuration of xilinx ml40x
aluOk
- alu operaciones basicas suma resta and or xor, complemento a 1 y a 2
pwm2
- modulo para implementar pwm
Xilinx_DDR
- 本文档对ISE开发环境利用MIG调用DDR2 IP CORE进行了进行了详细的介绍，对初学者很有帮助。其中FPGA芯片为Xilinx公司SP6 FPGA, DDR2 内存为Micron 公司的一款 R2 MT47H128M8 芯片。-This document calls ISE development environment using MIG DDR2 IP CORE conducted a detailed descr iption, very helpful for beginners.