资源列表
Experiment08
- FPGA源码，供初学者使用，时钟化和信号长度-GA source code, for beginners, clock and signal length
Exelixis-RRDR-2011-4
- IEEE Paper on Ethernet A Versatile UDP/IP based PC$FPGA Communication Platform -IEEE Paper on Ethernet A Versatile UDP/IP based PC$FPGA Communication Platform
udpip_literature
- Paper on UDP An analysis of FPGA-based UDP/IP stack parallelism for embedded Ethernet connectivity -Paper on UDP An analysis of FPGA-based UDP/IP stack parallelism for embedded Ethernet connectivity
Count_1sec
- 使用FPGA下載達成計數一秒鐘功能 以測試完成可以使用 -Use FPGA download count reached a second function can be used to test complete
zhuangtaiji
- 状态机 多种状态的转换 verilog语言编写-Convert verilog language write state machine multiple states
half_adder
- VHDL code for generating half adder
shift_right
- VHDL code for generaring shift register
d_flip_en
- VHDL code for generating D-flip flop
counter
- generating counter using VHDL
quartus9_tst
- 一个比较简单的基于CPLD的数码管显示程序，适合初学者学习，使用Verilog编写-A relatively simple CPLD-based digital tube display program, suitable for beginners to learn to write using Verilog
DS18B20
- 由于18B20时序要求严格，一般不建议采用niosii来实现对他的驱动。本人自己编写的基于NIOSII驱动函数，50MHz主频，保证可用，温度精确到0.0625度。-Due to stringent timing requirements 18B20 generally not recommended niosii to achieve his driver. I have written based on NIOSII driver function, 50MHz frequency, can
dac5686
- 在FPGA上编写的通过SPI总线配置外部DAC芯片DAC5686的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 -Configure external DAC chip DAC5686 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you