资源列表
Example-b8-5
- 四态的VCD文件，参数在0/1/X/Z之间变化，没有信号的强度信息-The four state VCD file, parameter changes between 0/1/X/Z, no intensity information of the signal
Example-b8-6
- Synplify Pro综合流程，体会Synplify Pro综合工具的使用方法与技-Synplify Pro synthesis process, and technology usage experience of Synplify Pro synthesis tool
da
- distributed arithmetic based fir filter implementation by xilinx using system generator
important
- importatn document for fir filter implementation by distributed arithmetic
gailiangban
- 基于fpga的平台，用verilog，写的一个可以表白的工具-can be use to show love
counter60
- this a counter. it can count from 0 to 50-this is a counter. it can count from 0 to 50
EDA
- 里面包含各种基于赛灵思公司的一些考试应用小程序及一个电梯控制系统的设计。-Which contains a variety of exams based on Xilinx some applets and an elevator control system design.
ZIDONGDIANTIKONGZHI
- 三层的电梯控制,具备显示，加速，以及开关门的延时等操作-Three elevator control, including a display, acceleration, and an operation switch gate delay and other
16_buzzer
- verilog语言，fpga学习源码,初学者易懂-verilog language, fpga learning source, beginners to understand
22_sos_system
- fpga源码，供初学者使用，sos编码原理-fpga source code, for beginners, sos coding theory
24_lcd_gui
- fpga源码，供初学者使用，GUI系统说明-fpga source code, for beginners, GUI System Descr iption
Experiment01
- FPGA源码，初学者使用，时序程序分析，整数乘法器-FPGA source code, for beginners to use, timing program analysis，Integer multiplier