资源列表
uartverilog
- 该文档为特权同学EMP240开发板上面的串口通信源码和相关资料-The documentation for the privileged students EMP240 development board the serial communication source code and related information
ex9_ps2
- 该文档为特权同学EMP240开发板上面的键盘操作，能够进行ps2键盘的操作，验证正常，源码和相关资料；-The documentation for the privileged students EMP240 development board above the keyboard operation, able to perform the ps2 keyboard operation, validation is normal, source code and related informa
verilogiic1121
- 该文档为特权同学EMP240开发板上面的iic的操作，实现的功能室通过两个按键进行控制iic的读写操作，通过数码管进行显示，验证正常，源码和相关资料；-The documentation for the privileged students EMP240 development board above the iic operation, realize the function of the room by two buttons to control the iic read and wr
verilogsram
- 该文档为特权同学EMP240开发板上面的SRAM的操作，该实验实现了对 SRAM 的每一个地址进行遍历读写操作， 然后比对读写前后的数据是否正确，最后通过一个 LED 灯的亮灭进行指示，验证正常，源码和相关资料；-The document for the privileged students EMP240 development board on the operation of the SRAM above, the experiment achieved to traverse the S
mult_piped_8x8_2sC_h1
- 這是由我自己寫的8位元乘法器,雖然不是最好的但是希望能提供同學們課業上的好幫助-It was written by my own 8 yuan multiplier, though not the best but hope to provide better help students on academic
Adder_16bit_2b
- 這是由我自己寫的16位元可處理2補數的加法器,希望能提供同學們課業上的好幫助-It was written by myself 16 yuan can handle two' s complement adder, hoping to provide better help students on academic
1.3V-default
- 這是一個適用於1.8V轉1.3V必迴路 在1Mhz頻率下 RLC各為 25m 4.7u 10u 給有需要的同學作為參考-This is one for 1.8V 1.3V will turn 1Mhz frequency RLC circuit at each 25m 4.7u 10u to needy students as a reference
alpha1_3_compensator
- 同為適用於1.8V轉1.3V必迴路 在1Mhz頻率下 RLC各為 25m 4.7u 10u 排除浮點數的int整數補償器 給有需要的同學作為參考-The same applies to 1.8V 1.3V will turn 1Mhz frequency RLC circuit at each 25m 4.7u 10u exclude floating point int integer compensation to needy students as a reference
ComparatorTestVersion
- 基於wire方式設計的補償器,但需外接DFF依照同學想做幾階的可在進行外加,Z^-1 需2個 Z^-2 3個依此類推.僅提供實做參考,實際參數需自行設計-Based on wire mode compensator design, but need to add DFF in accordance with the order of a few students want to be carrying plus, Z ^-1 need two Z ^-2 3 one, and so on. Pr
timing_sim
- 使用ModelSim对Altera设计进行时序仿真的简单操作步骤-Simple operation steps using the ModelSim timing simulation for Altera design
Example-b8-3
- 使用DO文件进行仿真的基本方法,包含基本操作步骤-The basic method of using DO file for simulation，include basic steps
Example-b8-4
- ModelSim的波形比较的功能可以将当前仿真与一个参考数据（WLF文件）进行比较，比较的结果可以在波形窗口或者列表窗口中查看-Comparison of the ModelSim wave functions , compare the results can be viewed on the waveform window or the list window