资源列表
GTKWave_ISim
- gtkwave simulator for fpga code
internal_reset.v
- code for internal reset in fpga
fft
- fft in verilog code for fpga
VGA
- vga显示硬件模块verilog语言编写，实现了一个动画显示，适合于初学者学习。-vga display hardware module verilog language to achieve an animated display, suitable for beginners to learn.
IO-timing-constrain-in-fpga
- 对FPGA的IO口的时序分析小结，能够详细理解其约束时序规则-FPGA timing analysis summary of IO port, capable of a detailed understanding of its timing constraint rules
IIC
- 硬件语言verilog实现IIC控制器，严格按照IIC协议编写硬件控制器行为及代码-Hardware language verilog realize IIC controllers, written in strict accordance with IIC protocol hardware controller behavior and codeHardware language verilog realize IIC controllers, written in strict acco
MVLSI_CBP_16.-FPGA-based-for-Implementation-of-Mu
- Paper on FPGA-based-for-Implementation-of-Multi-Serials-to-Ethernet-Gateway
divby4.5.v
- This Divider by 4.5.-This is Divider by 4.5.
lfsrupdwn.v
- This left shift register.-This is left shift register.
divby3.v
- This Divider by 3.-This is Divider by 3.
jkff_behav.v
- This is JK-FF in Behavioural Style.
UartLoop
- xilinx FPGA XC6LX9 串口通信程序 返回发送内容-xilinx FPGA XC6LX9 serial communication program returns to send content