资源列表
TCD1251
- 应用verilog语言，对TCD1251元器件进行驱动，以实现相应功能-To drive TCD1251 device
adconfig
- 一般AD模数转换器的VHDL配置程序，输出为14位串口输出，状态机实现的。-General AD ADC VHDL configuration program, the output is 14 serial output, the state machine implementation.
daconfig
- 一般DA模数转换器的VHDL配置程序，输入为14位串口输出，状态机实现的。-General AD ADC VHDL configuration program, the output is 14 serial output, the state machine implementation.
fir
- FIR滤波器的FPGA实现，串行移位算法，运行周期长但资源利用率低。-FIR filter FPGA, serial shift algorithm, but the long-running cycle of low resource utilization.
firtesmul
- 基于FPGA的FIR滤波器实现，并行乘法实现，运行速率快但占用资源多。-FPGA-based FIR filter, parallel multiplication achieve faster run rate but take up more resources.
iir
- 基于FPGA的IIR滤波器实现，运行周期短，占用资源多，-IIR filter FPGA-based implementation, operation cycle is short, take more resources,
fpgaai2c
- 包含I2C协议说明及运用verilog实现读写I2C器件功能-IT contains I2C protocol instructions and use verilog to achieve functional literacy I2C devices
usb3300_20081015.tar
- usb sourcecode in vhdl along with document explaining it.test bench also added.
zr36060.tar
- vhdlsource code for jpegpack
6.An-FPGA-Based-High-Speed-IEEE-754-Double-Precis
- An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier
TFT
- FPGA EP1C6Q208C8实验。使用FPGA直接控制TFT彩屏，达到显示RGB。有仿真波形。-FPGA EP1C6Q208C8 experiment. Use the FPGA control to display TFT screen, RGB. A simulation waveform.
traffic-light-vhdl-Quartus-II6.0
- 简单的交通灯vhdl程序 Quartus II6.0下的程序 包含图形仿真-easy traffic light vhdl Quartus II6.0