资源列表
UART(RS232)
- 用VERILOG语言实现的通用异步串行收发器（RS232收发器），波特率可设置，通讯稳定，已成功应用于实际项目。-VERILOG language with universal asynchronous serial transceivers (RS232 transceiver), the baud rate can be set, communication stability, has been successfully applied in actual projects.
water-LED
- 用VERILOG语言实现的LED流水灯实验，通过移位方法实现，代码简单实用。-VERILOG language with an LED light water experiment, achieved by shifting method, the code is simple and practical.
CRC
- 用VERILOG语言实现的CRC循环冗余校验码，已成功用于实际项目。-With VERILOG language of the CRC cyclic redundancy check code has been successfully used for actual projects.
Infrared-remote-control
- 用VERILOG语言实现的红外遥控实验，已成功用于实验用小飞机的飞行控制。-Experiment with infrared remote VERILOG language, has been successfully used in experiments with small aircraft flight control.
work_1
- spartan 3e-500 lcd 显示的数字钟，能显示年月日时分秒，以及星期还有闹铃时间，时间闹铃等可以自动调节，还有电台报时功能。星期模块有些许问题，调年月日的时候星期不会自动跳变，需要自己重新调，正常计时会自动跳变。-Spartan 3 e- 500 LCD display digital clock, can show minutes when (date) (month) (year), and week as well as the alarm time, time can aut
PCI_IF_AMCC-S5920.ZIP
- Design for PCI IF AMCC S5920
ADDA_2C5
- AD采集和DA转换，对于AD初学者是一个很好的学习例程。-AD and DA conversion, it is a good learning routines for learners
fs_re
- 超声波脉冲发射和计时程序，脉冲串个数和周期可设置-Ultrasonic pulse transmission and timing program，pulse sequence number and cycle can be set up
ModelSim-Settings
- 设置ModelSim仿真步骤,运用Quartus II 13.0 (32-bit) University Program VWF 波形文件编程功能后，使用ModelSim-Altera进行仿真。-Set ModelSim simulation steps, using Quartus II 13.0 (32-bit) University Program VWF programming function waveform file, use the ModelSim-Altera simulat
Middlefilter
- 基于FPGA的中指滤波器，使用verilog语言实现，仿真结果正常。-FPGA-based middle filter using verilog language, simulation results properly.
clock
- 数字时钟 LCD1602显示 可以校时。 编译环境QUARTUS II 7.2 -Digital clock LCD1602 display can be corrected. Compilation environment QUARTUS II 7.2
LCD1602-DRIVER(vhdl)
- LCD602的驱动器模块源代码 可直接使用 编译环境QUARTUS II 7.2-LCD602 drive module source code Can be used directly Compilation environment QUARTUS II 7.2