资源列表
mult_8b_for
- 本实验使用Verilog语言 通过FOR循环完成8bit乘法器功能，通过ISE仿真测试，可实现综合-Verilog language used in this experiment through the FOR cycle completed 8bit multiplier function, through the ISE simulation tests can be integrated
fifo_test
- FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
fir
- 利用Verilog语言编写的FPGA作为数字fir滤波器的程序，在编译器中调试通过，可以作为模块调用。-the model of fir digital cr which is written of verilog language.
parallel-fifo
- 利用Verilog语言编写的并行数据传输程序，在编译环境中编译通过。- the model of parallel data transmit which is written of verilog.
1204pointsFFT
- 1024点FFT VHDL实现,含有说明部分，自己好好理解，可自行修改-1024 point FFT VHDL realization that contain part of a good understanding of their own, they are free to modify
can_parts
- This the CAN bus controller for implementation inside any FPGA-This is the CAN bus controller for implementation inside any FPGA
Altera
- in file sare karie ,khodeto aziat nakon-in file sare karie ,khodeto aziat nakon......
KIT1234
- This used how to connect the DE2 kit for the external devices-This is used how to connect the DE2 kit for the external devices
lcd_B
- lcd module interfacing inintialization example
clock
- 用verilog实现的数字钟，已经在ACTEL公司的A3P030的开发板上成功运行-Digital clock with Verilog , successfully ran on the board of ACTEL A3P030
bcd-decoder
- 用Verilog实现的BCD译码器. 经Quartus||波形仿真无误 经硬件验证无误-BCD decoder Realized by Verilog
EP3C8020111219125810_ROM_OK5
- 采用DSP builder v9.1实现正交两路单频输出，已经在EP3C80上面跑通，经实际验证是正确的。此例程非常简洁明了，可以作为DSP builder的入门示例。里面已经包含了生成好的modelsim仿真示例和仿真结果。-Achieved using DSP builder v9.1 orthogonal two single-frequency output, has been run through the EP3C80 above, are proven to be correct.