资源列表
VHDLaddercode
- 为了给大家紧张的工作减轻点负担，我把带进位输入的8位加法计数器上传在此，希望大家支持-In order to alleviate the intense work we point the burden, I entered into the 8-bit adder counter From Here, I hope you will support
qicheweideng
- 一个汽车尾灯的控制的程序，eda课程设计必备 可以控制左转右转等功能-A car taillight control procedures, eda required curriculum design and other functions can be controlled左转右转
16X64dianzhen
- 16*64点阵程序，运用串行传输数据，移位寄存器接收数据，硬件电路连接简单-16* 64 lattice procedures, the use of serial transmission of data, receive data shift register, hardware circuits connected simple
VDHL
- Verilog的135个经典设计实例，直流电机控制，游戏机，三态总线，加法器，锁存器等-Verilog s 135 classic design example, DC motor control, video game consoles, three-state bus, adder, latches, etc.
Spartan3FPGA
- xilinx spartan3 FPGA的最准确权威的配置方法-xilinx spartan3 FPGA authority of the most accurate way to configure
ALU
- 此代码能高速实算术逻辑单元的功能，适合risc_CPU的设计。若有不足，请多多包含。-This code can be really high-speed arithmetic logic unit function, suitable for risc_CPU design. If insufficient, please contain.
8253
- With realize based on the FPGA programmable timer counter 8253 designs -With realize based on the FPGA programmable timer counter 8253 designs
FSM_Design
- 讲述了状态机的相关知识，文章为重英文，利用具体的例子讲述了VHDL中 的状态机-About the state machine of the relevant knowledge, the article for the re-in English, the use of specific examples described in VHDL State Machine
diyabiao
- moore状态机~~~ 用vhdl语言实现-moore state machine ~ ~ ~ using VHDL language
VerilogHDL
- 一本介绍VHDL的好书，可以让你很快的熟悉VHDL知识。-A good book to introduce VHDL, can let you quickly familiar with the VHDL knowledge.
mclk
- 基于多时钟的处理，在跨时钟域的处理上有优势-Based on Multi-clock processing, the cross-clock domain processing advantages
CPLD_FPGA
- 《CPLD_FPGA设计及应用》课件与实例- CPLD_FPGA design and application, with examples of courseware