资源列表
Synplify
- 华为synplify入门教程：Synplify快速入门-Huawei Synplify Tutorial: Synplify Quick Start
Triangle_Wave_generater
- 采用vhdl语言编程，基于quartus平台的三角波仿真。-Using VHDL language programming, based on the Quartus triangular wave simulation platform.
CPLDVHDLCODE
- CPLD VHDL CODE非常好的参考资料-CPLD VHDL CODE a very good reference
timer_0
- 计数器的FPGA控制程序，开发平台为ISE或者quartus-FPGA counter control procedures, development platform for the ISE or Quartus
onchip_memory_0
- 在线仿真调试的存储器代码，可在ISE或quartus下完成调试-Online simulation of the memory debugging code can be accomplished under the ISE or Quartus debugging
jtag_uart_0
- jatag在nios环境下的接口代码，可在ISE或quartus下完成调试-Nios jatag environment in the interface code, can be accomplished under the ISE or Quartus debugging
cpu_0
- cpu代码，可在ISE或quartus下完成调试-cpu code, can be accomplished under the ISE or Quartus debugging
niosII_system_cpu
- cpu代码，可在ISE或quartus下完成调试-cpu code, can be accomplished under the ISE or Quartus debugging
count_binary_0
- 二进制计数器的硬件代码，可在ISE或quartus下完成调试-Binary counter hardware code, available at ISE or Quartus to complete debugging
div_clk
- 主时钟为15.36MHz的带选通的8位输出分频器，可得到100Hz,120Hz,1kHz,10kHz的频率-Master clock for the 15.36MHz band strobe output 8-bit prescaler, can be 100Hz, 120Hz, 1kHz, 10kHz frequency
PCR
- 本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。-This procedure is in the transport stream during transmission of program the clock to carry out field testing and modification, using Verilog HDL language programming.