资源列表
fifo
- 此程序为存储器常用的FIFO（先入先出），程序中没有指明位宽，这样更适合于初学者进行套用-This process commonly used for the memory FIFO (FIFO), the procedure is not specified bit, so more suitable for beginners to apply
32-bit_multiplier_model
- 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
VHDL
- 一个实现整数分频的VHDL代码，只要把n设置成你所需要的分频的数值就行-A realization of an integer divider of the VHDL code, as long as the n set you need the sub-frequency values on the line
mux21a
- 二选一多路选择开关，实现对信号的采集，分类。-Second, the election more than one way selector switch, to achieve signal acquisition, classification.
chuankou
- 串口VHDL实现 -Serial Serial VHDL realization of VHDL
8ENCODE
- 8位优先编码器 verilog CPLD EPM1270 源代码-8-bit priority encoder verilog CPLDEPM1270 source code
traffic
- 模拟交通灯 verilog CPLD EPM1270 源代码-Simulation of traffic lights verilog CPLDEPM1270 source code
UART
- 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
S4_LCD_VHDL
- 基于ep1c6的vhdl的lcd控制程序实例 -Based on the VHDL ep1c6 the lcd control procedures examples
vhdl
- VHDL学习手册,适合初学VHDL者和在设计VHDL时有疑问者。-VHDL learning manual, suitable for novice VHDL and VHDL in the design of those who have doubt.
freq
- 数字频率计，七位计数，显示六位，带test模块-Digital frequency meter, seven counts, showed that six, with test module
100exampleofvhdl
- 100个VHDL例子，包括各种逻辑门、组合逻辑电路及时序电路-100 VHDL examples, including a variety of logic gates, combinational logic circuit and timing circuit