资源列表
CPU
- 16位简单cpu用VHDL语言实现。里面有好几个的》-16-bit cpu with a simple VHDL language. There are several of the "
miller
- 整个系统分为两个模块：检测模块和解码模块。检测模块主要完成从输入串行序列判断出A，B或C信号，并分别输出脉冲标志脉冲串Signal_A，Signal_B和Signal_C；同时，当检测到任一信号时，BIT_EN_temp输出一个高脉冲。解码模块根据检测模块输出的三个标志脉冲进行0/1解码，输出最终的密勒解码数据DOUT；同时，输出DATA_EN和BIT_EN两个标志信号。-The whole system is divided into two modules: detection module
spitoi2s3
- spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换-spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
immediate_divide_module
- 用组合逻辑实现循环除法器。稳定、安全、可靠。-Combinational logic loop divider. Stable, secure, and reliable.
Taiwan_VHDL_course_notes
- 台湾中正大学 VHDL语言培训教程，内容全面，浅显易懂，适合在校学生及专业人士参考-National Chung Cheng University in Taiwan VHDL language training course is comprehensive, easy to understand for students and professionals in the Reference
digitalclockvhdl
- EAD设计VHDL语言环境数字时钟数码管显示方案，包括时间设置、调整等。-VHDL language environment EAD design digital digital clock display, including time for setup, adjustment.
ca_gen
- 此Verilog程序产生用于GPS卫星导航信号的C/A码，输入信号有时钟、时钟使能、复位、给定的卫星编号，输出产生的C/A码。此程序在代码上进行优化，占用了更少的资源。-This procedure generated Verilog for the GPS satellite navigation signals C/A code, the input signal with the clock, clock enable, reset, given the satellite number,
IPcore
- FPGA 的各种 ip core 供大家参考-FPGA various ip core for your reference
LCD1602
- 用VERILOG HDL编写的LCD1602例程，很好用，欢迎指点-LCD1602 routines, written in VERILOG HDL useful, welcome advice
2step_iir_filter
- 2阶iir 2KHz陷波器Verilog源代码。-2-order iir 2KHz notch filter Verilog source code.
MAC
- Verilog code for MAC
MIPS
- MIPS处理器的组员大作业，可以直接运行，提交，环境是quartus-MIPS processor crew great job, you can run directly, the author, the environment is quartusII