资源列表
watch
- 基于verilog-HDL的电子秒表电路，采用quartusII72编译仿真，经下载测试通过。-Verilog-HDL-based electronic stopwatch circuit simulation using quartusII72 compiled by downloading the test.
part2
- Altera DE2 开发板试验3 第2部分VHDL答案-Altera DE2 Lab3 Part2 VHDL Answer
parity_and_CRC
- 奇偶校验和循环冗余检测的Verilog代码，很好，和大家一起学习-Parity and cyclic redundancy detection of Verilog code, very good, and we will study together
yima1
- 本程序是在Xilinx ISE上编写的，它是（7,3）码的另外一种译码方法。里面有源程序和用以仿真的测试文件-This program is written in the Xilinx ISE, it is another (7,3) code decoding method. Source and for the simulation of the test file inside
ecp233_1
- elliptic curve processor b-233, include test bench & test vector.
DE2_i2sound_example
- 基于FPGA I2C总线的音频处理系统设计实现-FPGA I2C bus-based audio processing system design and implementation
DPLL
- 90度锁定的数字锁相环的设计的VHDL源代码-The VHDL code of Digital Phase-Locked Loop Based on CPLD
spartan3e_spi
- 本程序可以再spartan3e的板子上实现利用SPI协议实现对flash ID号的读取。-The program can achieve then spartan3e board SPI protocol to read flash ID number.
6_DigTub
- FPGA，VHDL 语言 静态点亮一位数码管，适用于所有FPGA芯片，VHDL源程序！-FPGA, VHDL language static lit a digital control applies to all FPGA chip, VHDL source code!
原代码
- 8051核的vhdl原代码。-8051 core VHDL source code.
verhdl95
- vhdl