资源列表
up_test
- 基于vhdl语言的源代码，用于检测信号的上升沿，多用于同步时钟-Vhdl source code based on the language used to detect the rising edge, used for synchronous clock
Crack_Altera_Quartus61.0-9.1
- Crack_Altera_Quartus61.0-9.1.rar license-Crack_Altera_Quartus61.0-9.1.rar license!!!
Verilog
- FPGA经典例子，可以让大家更好的学习Verilog HDL-Classic example of FPGA, allowing you to better learn Verilog HDL
nios-ii
- ALTERA 公司NIOSII收集的一些资料，对学习NIOSII应该很有帮助-NIOSII ALTERA company collected some information should be helpful in learning NIOSII
altera_bootmethods
- altera u-boot niosii用户使用手册-altera u-boot niosii
a_vhdl_8253_timer_latest.tar
- 一个apb总线控制8253的verilog源代码，符合标准的amba 2.0的总线规范-A apb bus control 8253 of the verilog source code, amba 2.0 standard bus specification
four_adder
- 应用一位全加器的VHDL语言，创建一位全加器符号，用原理图完成四位全加器-Application of a full adder VHDL language, to create a full-adder symbol, with the principle of the completion of four full adder diagram
spartan_LCD
- 实现了spartan-3E LCD的显示驱动，可以通过LCD观察数据变化-Realize the Spartan-3 E LCD display driver, can pass LCD observation data changes
shipintuxiang
- 基于VHDL，实现视频图像的行列计数器，已经调试仿真通过可用.-Based on VHDL, the ranks of video image counter, has been simulated through the available debugging.
Aoscilloscopebasedonmsp430andFPGA
- 一款基于msp430fg4618单片机及ep1c6q340c8 fpga的简易示波器实现方案-A msp430fg4618 Microcontroller and ep1c6q340c8 fpga based on the simple realization of the program oscilloscope
20100629001
- 基于NetFPGA，实现路由转发的工程。在此工程中，可以修改路由表，实现多功能的路由功能。-Based NetFPGA, forwarding the project to achieve routing. In this project, can modify the routing table, routing capabilities to achieve multi-functional.
miller
- miller码编码模块的verilog程序，修正miller码编码模块的程序，完成miller码编码模块功能。-miller module verilog coding procedures, the amendment procedures miller coding module to complete the miller coding module function.