资源列表
xapp1076
- Implementing Triple-Rate SDI with Spartan-6 FPGA GTP Transceivers
DAY07
- verilog 编写的查询法和线反转法举证键盘实例程序-verilog matrix—key
MySDTEST
- 读取F16文件系统的SD卡里面的bmp文件-To read bmp file of F16 file system on SD card
uartfifo
- 串口收发程序，VHDL版本，适用于ALTERA的CPLD -Serial transceiver procedures, VHDL version
lanqiu24s8
- 篮球24s计时。计时器递减计数到零时，数码显示器显示‘0’并停止，同时发出报警信号-basketball 24 seconds
cordicDDS
- Cordic算法实现DDS的Verilog 源码,14位精度，非常实用的。-DDS algorithm Cordic the Verilog source code, 14-bit accuracy, very practical.
USB2UART
- usb串口通信的固件程序与FPGA控制程序-usb serial communication firmware and FPGA control program
FPGA-digital-clock-design
- 运用顶层设计思路设计好各个底层文件（VHDL代码），对各个底层文件进行功能仿真；采用原理图或者文本方法来实现顶层文件的设计，对顶层文件进行功能真仿真。在顶层文件功能仿真正确之后，把顶层文件下载到实验箱的FPGA里边去，验证电路功能是否正确。具体时间用6位数码管来显示，具有整点报时功能. -Designed various underlying file using top level design (VHDL code), on functional simulation of variou
nlint-user-manual nlint verilog vhdl 规则库
- nlint verilog vhdl 规则库 支持自定义 批量检查代码中bug -nlint a eda debug tool software rules ， user define rules ， verify code automatic
i2c_rx8025
- lm3s读取r8025芯片的代码，RTC序列-Lm3s read r8025 chip code
mygui_v6
- 在NiosII系统下成功移植uc/GUI3.98。使用的硬件条件是DE2开发板+TRDB-LTM，实现分辨率400*240，332颜色模式，并且可以触摸。-In NiosII system successfully transplanted the uc/GUI3.98.The used hardwares conclude DE2 development board and TRDB-LTM.It s display resolution is 400* 240,and the color m
This VHDL code pertains to the DCO model
- code.doc C.1 DCO LEVEL 2 This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between