资源列表
bono_evb_cpld_1.2.rar
- sources of CPLD (fpga) from freescale i.MX27 Avanced Designe System Develpment Kit board,sources of CPLD (fpga) from freescale i.MX27 Avanced Designe System Develpment Kit board
CODE.rar
- AHB总线下的slave ram的verilog代码,AHB bus slave ram verilog
脉宽测量程序源代码
- 脉宽测量：可以用来测量脉冲宽度，周期技术信号显示从00到FF，共16x16位,Pulse width measurement: can be used to measure pulse width, cycle technology signals from 00 to FF, a total of 16x16-bit
cy7c1371c_vhdl_10.zip
- cy7c1371c ZBT SRAM 的仿真模型，VHDL编写。,the simulate model of cy7c1371c,VHDL language.
IS-95/CDMA2000基带成形滤波器的实现
- IS-95/CDMA2000基带成形滤波器的实现 IS-95滤波器的实现： 本次设计采用转置型结构，并用展开技术将字串行架构转换成字并行处理架构，从而提高运行的速度。本次设计中采用展开因子J=4的展开转换技术。设输入数据为filter_in，输出数据为filter_out，则其展开因子J=4的并行处理系统如下图所示 ,IS-95/CDMA2000 base-band filter shaping to achieve IS-95 filter to achieve: the desig
8B-10B.rar
- 一种新的8B-10B编解码硬件设计方法，希望对您的工作有所帮助。,A new codec 8B-10B hardware design, and I hope to be helpful to your work.
HPI.rar
- 基于CPLD/FPGA器件的HPI接口程序 难能可贵,HPI based on CPLD/FPGA instrument
DE2_70_pin_assignments.rar
- de2-70的引脚配置文件，给各位急需分享一下，用于fpga的开发,de2-70 of the pin configuration files, to share that much-needed for the development of fpga
delay_early_gate.rar
- 超前滞后锁相环，可以精确的是想符号同步的 采用V_LOG代码编写 可以直接使用,Lead and lag phase-locked loop can be accurate is to synchronize the use of symbols V_LOG code can be directly used to prepare
MaxplusII.rar
- 本电子书详细地介绍了VHDL语言开发环境 Max+plus II 软件的使用方法，让新手很快学会如何使用本软件,This book describes in detail VHDL language development environment Max+ plus II software to use, so that novices will soon learn how to use the software
BFD.rar
- 针对SOC测试环优化的BFD算法源代码。得到各个IP核在不同TAM宽度下的测试时间。,BFD Algorithm source code based SOC wrapper optimization
DEX_jiangjie.rar
- 自动售货机 dex通信协议 讲解 原创资料 我确定,Vending machine dex data communication protocol on the original I' m sure