资源列表
shuma.rar
- 数码管动态显示程序，verilog的，已经调试成功,verilog
DE2_70_LTM_CCD.zip
- A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM. ,A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.
cs555.rar
- 这是一个用VHDL语言写的用状态机控制cs5550进行AD转换的代码，里边包含用逻辑分析仪进行分析的文件。具有很强的可移植性。,This is a work written in VHDL language using state machine control cs5550 for AD conversion code inside that contains the logic analyzer with an analysis of documents. Are highly portab
filter_verilog.rar
- 用verilog实现的低通滤波器，输入输出精度为64位，并附有测试程序。,Use verilog to achieve a low-pass filter, input and output accuracy of 64, together with testing procedures.
adder.rar
- 一位全加器可由两个一位半加器与一个或门构成，该设计利用层次结构描述法，首先设计半加器电路，将其打包为半加器模块；然后在顶层调用半加器模块组成全加器电路,A full adder can be two a half-adder and an OR gate structure, the design is the use of hierarchical descr iption method, first of all the design half-adder circuit, be packa
VHDL_FIR_PRO_scr.rar
- 可编程的FIR滤波器VHDL实现，只要输入FIR的阶数以及系数，就可在FPGA中实现FIR滤波器,Programmable FIR filter VHDL implementation, simply enter the order number as well as the FIR coefficients, we can implement FIR filters in FPGA
eeprom_i2c.tar.gz
- I2C EEPROM verilog simulation model,I2C EEPROM verilog simulation model
Nios2_H264-AVC_DEC.rar
- 在Altera开发环境下采用Nios II和硬件加速实现H.264解码的系统方案,The solution uses the Nios II development environment and hardware accelerate to implement H.264 decoding under Altera platform
viterbi_for_bch.rar
- Viterbi based trellis decoder for (7,4) - binary BCH code,Viterbi based trellis decoder for (7,4)- binary BCH code
led.rar
- 跑马灯 简单实用很适合初学者 希望对大家有用,Marquee is simple and practical very suitable for beginners want to be useful to everyone
synplify_ug.zip
- Synplify user s guide，很好的synplify用户手册，对综合入门很有帮助。全英文，官方资料,Synplify user' s guide, a good synplify user manual, on the consolidated entry helpful. In English, the official data
sdram_pci.rar
- 基于SDRAM的PCI采集程序，PCI9054控制器+SDRAM控制器Verilog源代码，，已经SignalTap调试通过。,SDRAM PCI-based acquisition program, PCI9054 Controller+ SDRAM controller Verilog source code, has SignalTap through debugging.