资源列表
VHDL源代码4
- VHDL与源代码包-and VHDL source code
循环冗余校验码
- 循环冗余校验码(试验报告)-Cyclic Redundancy Check (pilot reports)
数字频率计(试验报告)
- 数字频率计(试验报告)适合初学者参考-Digtal Frequency Test(experiment report) suit Raw recruit reference
7状态机设计
- 这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！-This is the "state machine design (the scr ipt)", and I hope to learn VHDL is there to help the students, thank you!
VHDL设计进阶
- 这是“VHDL设计”讲稿，希望对初学者有用，-"VHDL design" scr ipt, useful for beginners, thank you! !
ieee-std-1364
- 做EDA的，就不用介绍这个文件了吧，IEEE1364标准（开放）。-done, would not have introduced the document on the bar, IEEE1364 standard (open).
IP core
- VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
verilog2000
- verilog2000更新部分，请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support
Verilog HDL Examples
- verilog的入门级别的例子（转载）-Verilog entry-level examples (reproduced)
fpga学习中常用的缩略语
- fpga学习中常用的缩略语-commonly used abbreviations
max2work
- verilog编写实用多功能电子表-Verilog prepared practical multi-function electronic Table
MYCPU2.0
- 用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU